1. Field of the Invention
The present invention relates to a solid-state image pickup device.
2. Related Background Art
With the recent remarkable progress in the semiconductor technology, the solid-state image pickup device represented by the CCD has shown significant improvement in performance and has been applied in various products such as facsimile and scanner. In such trend, there are emerging more stringent requirements for the solid-state image pickup device, not only for higher performance, such as a higher sensitivity or a higher resolving power, but also for drivability with a lower voltage. As a result, in the field of CCD, there have appeared products drivable with a 5 V power source and developments are being made to achieve drivability with a lower voltage.
Also with a higher sensitivity, there is expected the application for a photodetector capable of detecting very weak light that has not been detectable and effecting signal processing on thus detected light.
Also as a highly advanced ability of the solid-state image pickup device, there is required an ability to detect whether a certain light is present, and, upon detection of the light, to provide a detailed image output of the portion of such light.
An example of the conventional bipolar solid-state image pickup device is shown in FIGS. 1 and 2. FIG. 1 is an equivalent circuit diagram of a unit pixel, which is composed of an NPN bipolar phototransistor 14, a pixel separating-resetting PMOS transistor 11, a base potential control capacitor 13, a three-value pulse supply terminal PR, and a bias reset supply terminal VBR.
FIG. 2 shows a solid-state image pickup device consisting of a one-dimensional array of four bipolar photoelectric converting elements explained above, while a three-value pulse from a three-pulse terminal 1 is in the LOW level state, a reset pulse is supplied from a reset terminal 2 to render the PMOS transistors 11 conductive, whereby the NPN transistors 14 are reset. When the three-value pulse from the three-value pulse terminal 1 is shifted to the MIDDLE level state, the gate-source voltage VGS of the PMOS transistors 11-1 to 11-4 becomes lower than the threshold value Vth of the transistors, whereby these transistors are rendered non-conductive and a first resetting operation is completed.
Then, when the reset terminal 33 is shifted to the high level state, the NMOS transistors 22 are rendered conductive and the emitters of the NPN transistors 14 are reset. Subsequently the three-value pulse terminal 1 is shifted to the high level state, whereby the bases of the NPN transistors 14 are shifted to the floating state through the control capacitances 13, and, when the three-value terminal 1 is shifted to the middle level, there is initiated the accumulation of the photon charges by photoelectric conversion. Subsequently, after the lapse of a predetermined time, a transfer terminal 32 and the three-value pulse terminal 1 are shifted to the high level state, whereby the NMOS transistors 23 are rendered conductive, and the charges accumulated in the bases are transferred to transfer capacitances 24 by the application of a high-level pulse to the reset terminal 3. Then a horizontal shift register 29, receiving a start pulse 30 and scanning pulses 31, releases scanning signals for rendering scanning NMOS transistors 25 conductive in succession, whereby the charges of the accumulating capacitances 24 are in succession transferred to an output line 42 and released to an output terminal 28 after amplification in an amplifier 41. After each signal output from the accumulating capacitance 24, a reset pulse is applied to the reset terminal 27 whereby the remaining charge on the output line 42 is dissipated to the ground through an NMOS transistor 26. The image of a line can be released through the above-explained operations, and the function as an area sensor can be achieved by repeating the above-explained operations in combination with a movement of the sensor.
As explained in the foregoing, the signals of the different pixels are once read into the transfer capacitances C24-1 to C24-4 and are then serially transferred to the output terminal by the function of the scanning circuit. The gain GT and the output voltage V0 at the transferring operation are represented by:
GT=(CT)/(CT+CH) (i=1, 2, . . . )xe2x80x83xe2x80x83(1)
V0=(CTVi)/(CT+CH) (i=1, 2, . . . )xe2x80x83xe2x80x83(2)
wherein
CT: capacity of transfer capacitances C24-1 to C24-4;
CH: parasite capacitance including the capacity of the output line; and
Vi: signal voltage retained in the transfer capacitances C24-1 to C24-4.
The capacitance CH is composed of the drain capacitance and the gate overlapping capacitance of the scanning transistors 25-1 to 25-4 and the resetting transistor 26, the input capacitance of the output amplifier and the parasite capacitance of the output wiring, and is heavily dependent on the number of pixels and the manufacturing process. It is in the order of several picofarads in case of several hundred pixels. On the other hand, CT is composed of the capacitances of the MOS device and of junctions, and is designed in the order of several picofarads in the actual integrated circuit.
Consequently the above-mentioned transfer gain is usually in the order of 0.3 to 0.4, and a larger gain leads to an increased cost because of an increased chip size. Consequently a gain of several times is applied in the subsequent stages if a larger signal value is required, but a sufficient gain is difficult to obtain in a low-voltage drive because of the limited input/output dynamic range.
Also the image taking will not be required if the brightness of the image is low and does not reach the sensitivity of the pixels, but, if the image has a certain level of brightness, it is often required to obtain details of such lighted area. The image detection with a line sensor under such condition requires the scanning operation over the entire pixels, thus requiring a long time for the scanning operation with a large power consumption, and, if such brightness appears instantaneously, it is difficult to detect such instantaneous bright area.
Also in the configuration shown in FIG. 2, the time for one cycle is principally used for pixel resetting, signal read-out and serial signal transfer, and the significant part is usually used for the serial transfer. This time becomes longer with the increase in the number of pixels, and, in case of an area sensor with plural lines, most of the cycle time is occupied by the signal transfer time. Consequently, in the application for a detector for detecting the presence or absence of an image at a high speed, it is an important issue how to reduce this time.
The present inventors have disclosed, in the Japanese Patent Laid-open Application No. 6-268920, that this signal transfer time can be reduced by releasing a signal averaged over plural pixels. However, in the above-mentioned invention, though the signal averaging is easy in the horizontal direction of the area sensor, it can normally be made for 2 to 4 pixels in the vertical direction, as a larger averaging leads to an increase in the chip size. Consequently an inexpensive high-speed detector has been extremely difficult to realize with an area sensor.
An object of the present invention is to provide a solid-state image pickup device provided with an array of plural blocks each of which is composed of two or more pixels, wherein the outputs of said block are connected in common, respectively through amplifier means.
Another object of the present invention is to provide a solid-state image pickup device capable, for resolving the above-mentioned drawbacks, of outputting both an output signal obtained by pre-processing of the signals of the pixels and an output from each pixel, wherein the above-mentioned pre-processed output signal is output through output means for the signal of each pixel.
Still other objects of the present invention, and the features thereof, will become fully apparent from the following description which is to be taken in conjunction with the attached drawings.